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Page 73 highlights Alignment and Adjustmens 6.6 How to use EDC (Engine Diagnostic Control) Mode EDC Mode is feature that allows the engineer to check the condition of the print engine. It can check the operating condition of the motors, sensors, solenoids and clutches, measure the High Voltage from the HVPS and check the operation of the fuser and LSU. 6.6.1 Enterence When trying to check the CLP-300 Series EDC Mode, additional EDC execution program needed. Procedure of EDC Mode operation a) First, turn on the Power of Printer, wait until Ready state b) In this state, Run the EDC program on the computer c) After that, click the menu of screen d) Then appears on the initial screen e) Should you get out of this program, press Exit of screen 6.6.2 Keys Key Exit Update LCD Menu Left/Right arrow Enter Upper level Discription Close program Update value (ex: sensor value) Move to the top menu Move test item Start testing or select Sub-item Stop testing or the upper menu 6.6.3 EDC Map Service Manual Samsung Electronics 6-13.
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A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed. What is claimed is: 1. A programming method of a flash memory device having memory cells, comprising: programming selected memory cells according to loaded data; sensing states of the programmed memory cells and firstly latching the sensed states; and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the firstly latched states, before determining whether the selected memory cells have been properly programmed. The method of claim 1, wherein a programming operation is terminated in response to the program-inhibited memory cell among the selected memory cells being programmed. The method of claim 1, further comprising, in response to the program-inhibited memory cell among the selected memory cells having not been programmed: secondarily latching the sensed states; and determining whether the selected memory cells have been properly programmed with reference to the firstly and secondarily latched states, wherein the firstly latched states are complementary to the secondarily latches states to programmed memory cells. The method of claim 1, further comprising: terminating a programming operation in status fail, without determination of whether the selected memory cells have been properly programmed, in response to the program-inhibited memory cell of the selected memory cells being programmed. CROSS-REFERENCE TO RELATED APPLICATIONS This U.S.
Non-provisional patent application claims the benefit under 35 U.S.C. §119(a) of Korean Patent Application No. 2008-66540, filed on Jul. 9, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1.
Field of the Invention The present general inventive concept disclosed herein relates to semiconductor memory devices, and more particularly, to a flash memory device and programming method thereof. Description of the Related Art Flash memory devices are generally programmed through program loops having data loading, programming, and verifying periods. Referring to FIG. 1, which illustrates a programming procedure of a flash memory device, data to be programmed (hereinafter referred to as ‘program data’) is loaded into the flash memory device (e.g., into a page buffer of the flash memory device) from an external device (e.g., memory controller) during the data loading period. The loaded data is programmed in selected memory cells during the programming period.
During the verifying period, the flash memory device determines whether the selected memory cells have been programmed with the loaded data. In the flash memory device, the memory cells are erased before the programming procedure. Typically, an erased state of a memory cell is defined as data ‘1’.
Therefore, in such an instance, selected memory cells will be maintained in a same state as the erased state when they are to be programmed into data ‘1’. Determining that selected memory cells have been programmed into data ‘1’ is accomplished by reading data bits from the selected memory cells and determining whether the read data bits are all conditioned in a program pass state (e.g., data ‘1’).
For example, if data ‘0’ is properly programmed into selected memory cells, as shown in FIG. 1, the loaded data ‘0’ will be changed into data ‘1’ during the verifying period. If data ‘1’ is properly programmed into selected memory cells, as shown in FIG. 1, the data ‘1’ will be maintained without change during the verifying period. If the read data bits are all detected as being properly programmed, and therefore reflected as data ‘1’ during the verifying period, the programming operation is terminated as being status pass (or program pass). According to the aforementioned mode for programming, as shown in FIG. 2, although memory cells to be program-inhibited are programmed into data ‘0’, data bits read out from selected memory cells will be determined as being in program pass (i.e., data ‘1’).
In other words, as shown in FIG. 2, if the selected memory cells to be program-inhibited are maintained on the erased state (CASE 2) or if all selected memory cells are properly programmed (CASE 1), the programming procedure will be terminated as being status pass. This means data is falsely stored in the memory cells. As a result, even though the programming operation is terminated as status pass, a read error can be caused therefrom.
SUMMARY The present general inventive concept is directed to a flash memory device capable of improving the reliability and a programming method thereof. Additional aspects and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept. The foregoing and/or other aspects and utilities of the present general inventive concept may be achieved by providing a programming method of a flash memory device having memory cells, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the firstly latched states, before determining whether the selected memory cells have been properly programmed. The foregoing and/or other aspects and utilities of the present general inventive concept may also be achieved by providing a flash memory device including a memory cell array having memory cells arranged in rows and columns, a reading/writing circuit configured to provisionally reserve data to be stored in the memory cell array and program selected ones of the memory cells of the memory cell array in accordance with the reserved data, and a control logic circuit configured to control the reading/writing circuit. The reading/writing circuit may sense states of the programmed memory cells and firstly latches the sensed states.
The reading/writing circuit may output a first verification data indicating whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the program-inhibited memory cell among the selected memory cells has been programmed. According to the present general inventive concept, the flash memory device may be improved in reliability by determining whether memory cells to be program-inhibited have been properly programmed. A further understanding of the nature and features of the present general inventive concept herein may be realized by reference to the remaining portions of the specification and the attached figures. BRIEF DESCRIPTION OF THE DRAWINGS These and/or other aspects and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: FIGS. 1 and 2 are diagrams illustrating a programming procedure of a flash memory device; FIG. 3 is a block diagram illustrating a flash memory device according to an embodiment of the present general inventive concept; FIG.
4 is a block diagram illustrating a page buffer of the reading/writing circuit illustrated in FIG. 3 in accordance with an embodiment of the present general inventive concept; FIG.
5 illustrates a circuit diagram of the page buffer of FIG. 4 in accordance with an embodiment of the present general inventive concept; FIG. 6 illustrates a circuit diagram of the page buffer of FIG. 4 in accordance with another embodiment of the present general inventive concept; FIG. 7 is a flow chart illustrating a programming method of the flash memory device in accordance with an embodiment of the present general inventive concept; FIG.
8 is a diagram illustrating state variations of the registers during the programming operation by the present general inventive concept; FIG. 9 is a flow chart illustrating a programming method of the flash memory device in accordance with another embodiment of the present general inventive concept; FIG. 10 is a block diagram illustrating a computing system with the flash memory device according to the present general inventive concept; and FIG. 11 is a block diagram illustrating a memory system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept by referring to the figures.
The present general inventive concept may, however, be embodied in different forms and should not be constructed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to explain different utilizations of the general inventive concept so that this disclosure will be thorough and complete, and will fully convey the scope of the present general inventive concept to those skilled in the art. 3 is a block diagram illustrating a flash memory device 1000 according to an embodiment of the present general inventive concept.
The flash memory device 1000 according to the present general inventive concept may be, for example, a NAND flash memory device. But the present general inventive concept should not be construed as being restricted to such a NAND flash memory. As illustrated in FIG.
3, the flash memory device 1000 according to the present general inventive concept may be comprised of a memory cell array 100, a row selector 200, a reading/writing circuit 300, a detection circuit 400, and a control logic circuit 500. The memory cell array 100 includes pluralities of memory cells arranged on intersections of rows (e.g., word lines) and columns (e.g., bit lines). The memory cells may be arranged to form pluralities of NAND strings. Each memory cell may be configured to store single-bit or multi-bit data. Each memory cell may be formed in a unit having a charge storage layer or variable resistance. However, those ordinarily skilled in the art will understand that the present general inventive concept is not restricted hereto regarding a type of nonvolatile memory cell. The memory cell array 100 may be configured in a 2-dimensional (i.e., plane) or 3-dimensional (i.e., vertical) structure.
The row selector 200 may be controlled by the control logic circuit 500, and selects rows of the memory cell array 100. The reading/writing circuit 300 may be controlled by the control logic circuit 500, and may be configured to write/read data into/from the memory cell array 100. The detection circuit 400 may be controlled by the control logic circuit 500, and may determine whether program-inhibited memory cells have been programmed in accordance with data bits loaded into the reading/writing circuit 300 and data bits read through the reading/writing circuit 300. Further, the detection circuit 400 also may determine whether memory cells have been properly programmed in accordance with data bits read by way of the reading/writing circuit 300. This operation will be discussed in more detail later in this description.
4 is a block diagram illustrating a portion of the reading/writing circuit 300 shown in FIG. 3 in accordance with an embodiment of the present general inventive concept, and FIG. 5 illustrates a circuit diagram of a page buffer 301 of FIG. 4 in accordance with an embodiment of the present general inventive concept. For convenience of description, FIG. 4 illustrates the page buffer 301 of the reading/writing circuit 300 in correspondence with a single bit line. Referring to FIG.
4, the page buffer 301 may include a load 310, first and second registers 320 and 330, a dump 340, a discharge circuit 350, and a data output circuit (DOC) 360, operating in response to control by the control logic circuit 500. The load 310 may be connected to a sensing node SN, supplying a sensing current to a bit line. The first register 320 may be configured to provisionally store data to be programmed.
Data held in the first register 320 may be transferred to the second register 330 through the dump 340. The discharge circuit 350 may operate to change data, which is stored in the second register 330, in accordance with a voltage of the sensing node SN.
The data output circuit 360 may output data from the second register 330 to a data line 302, during a verifying operation, or may output a combination of data from the first and second registers 320 and 330 to the data line 302. The load 310, the first and second registers 320 and 330, the dump 340, the discharge circuit 350, and the data output circuit 360 can be configured as shown in FIG. But the page buffer 301 is not limited to the features illustrated in FIG. 5 in organization. An operation of the page buffer 301 illustrated in FIG. 5 will be discussed in more detail later in this description.
According to another embodiment of the present general inventive concept, as illustrated in FIG. 6, a data output circuit 360′ may further include an NMOS transistor M 16.
In this case, the NMOS transistor M 16 may be activated after precharging the data line 302, in order to provide a uniform capacitive load while precharging the data line 302. 7 is a flow chart illustrating a programming method of the flash memory device in accordance with an embodiment of the present general inventive concept, and FIG. 8 is a diagram illustrating state variations of the registers during the programming operation by the present general inventive concept. The programming method according to this embodiment will now be described in more detail in conjunction with FIGS. The description will discuss a programming operation that will be carried out through a single program loop. The described operations S 110˜S 170 are included in this single program loop. The flash memory device according to the present general inventive concept utilizes an incremental step-pulse programming (ISPP) scheme by which a program voltage increases by a predetermined increment every repetition of the program loop.
Before discussing various components of FIGS. 5-6 and 8 along with the flow chart of FIG. 7, the operations of the flow chart will be described with reference to FIG.
The program data may be loaded into the reading/writing circuit 300 in operation S 100. The loaded program data may be programmed into selected memory cells in the memory cell array 100 in operation S 110.
After this programming operation, a verify-reading operation may be performed to determine whether selected memory cells have been successfully programmed in operation S 200. The verify-reading operation S 200 may include a sensing period (S 120), an inverse latching period (S 130), and a normal latching period (S 140). Afterward, it may be determined whether a program-inhibited memory cell has been inadvertently programmed in operation S 150. If it is determined in operation S 150 that a program-inhibited memory cell has been mistakenly programmed, the programming operation is designated as a status fail and the programming procedure is ended in operation S 190. If it is determined in operation S 150 that a program-inhibited memory cell has not been detected as being inadvertently programmed, it may be determined whether a selected memory cell has been properly programmed in operation S 160. If it is determined that the selected memory cell has been properly programmed in operation S 160, the control logic circuit 500 arranges a result of the programming operation to status pass and terminates the programming procedure in operation S 180.
If it is not determined that the selected memory cell has been properly programmed in operation S 160, it is determined whether a current count of the program loop has reached the maximum loop count in operation S 170. If the current count of the program loop is determined to have reached the maximum, the programming operation is designated as a status fail and the programming procedure is ended in operation S 190. If the current count of the program loop has not reached the maximum, the procedure returns to operation S 110. These operations will now be described in greater detail, including a discussion of some of the components which may be involved in the operations.
At the beginning of the programming procedure, a latch node LN 3 of the second register 330 may be first initiated to be high level. Thereafter, program data (i.e., data to be programmed) may be loaded into the reading/writing circuit 300 (S 100).
For instance, if a value of program data is ‘1’, data input signals DI and nDI are input from the control logic 500 with high and low levels respectively and a control signal CTRL 5 goes to high level. Then, a latch node LN 1 of the first register 320 is set on high level (i.e., logical ‘1’). Conversely, if the value of program data is ‘0’, data signals DI and nDI are input with low and high levels respectively and the control signal CTRL 5 goes to low level. In this case, the latch node LN 1 of the first register 320 is set on low level (i.e., logical ‘0’).
Data loaded into the first register 320 is transferred to the second register 330 through the dump 340. To perform this transfer of the loaded data, control signals CTRL 2 and CTRL 6 are activated to high levels. If the latch node LN 1 of the first register 320 is set to high level, an NMOS transistor M 10 of the dump 340 is turned off. During this operation, although the control signals CTRL 2 and CTRL 6 are activated to high levels, a latch node LN 3 is maintained on high level.
Conversely, if the latch node LN 1 of the first register 320 is set to low level, an NMOS transistor M 10 of the dump 340 is turned on. During this operation, when the control signals CTRL 2 and CTRL 6 are activated to high levels, a latch node LN 3 is changed from high level to low level. Through this described process, data loaded in the first register 320 is dumped into the second register 330. 8 illustrates logical states of the latch nodes LN 1 and LN 3 of the registers 320 and 330 by the data loading and dumping procedure.
Specifically, if the value of the program data is logical ‘0’, both LN 1 and LN 3 are set to low level after the data loading and dumping procedure, and if the value of the program data is logical ‘1’, both LN 1 and LN 3 are set to high level after the data loading and dumping procedure. Next, data held in the second register 330 may be programmed into selected memory cells (S 110). When the data stored in the second register 330, i.e., the level set in the latch node LN 3, is set on low level (i.e., logical ‘0’), selected memory cells may be programmed by a well-known mechanism (e.g., self-boosting). A physical mechanism of programming memory cells is well known by those skilled in the art, so will not be further described. After completing the programming operation, a verify-reading operation may be conducted to determine whether the selected memory cells have been successfully programmed (S 200). According to the flash memory device 1000 of the present general inventive concept, the verify-reading operation may be carried out by including a sensing period (S 120), an inverse latching period (S 130), and a normal latching period (S 140). The verify-reading operation S 200 will now be described in more detail.
During the sensing period (S 120), according to whether a selected memory cell has been successfully programmed, its corresponding bit line, i.e., the sensing node SN, is set on high or low level. For instance, if the value of the program data is ‘0’ and a selected memory cell has been properly programmed to have a desired threshold voltage, its corresponding bit line, i.e., the sensing node SN, is set on high level during the sensing period (S 120). Meanwhile, if the value of the program data is ‘0’ and a selected memory cell has not been programmed in the desired threshold voltage, the corresponding bit line, i.e., the sensing node SN, is set on low level during the sensing period (S 120). Otherwise, if the value of the program data is ‘1’, the corresponding bit line, i.e., the sensing node SN, is set to low level. Although the value of the program data is ‘1’, a selected memory cell can still be programmed. In this case, the bit line, i.e., the sensing node SN, is set to high level. The sensing node SN is set on high level, regardless of loaded data (i.e., logical ‘1’ or ‘0’), when a selected memory cell thereof is programmed to have the desired threshold voltage.
But the sensing node SN is set on low level in response to a selected memory cell thereof corresponding to data ‘0’ having not been programmed in a desired threshold voltage or in response to the selected memory cell being a program-inhibited memory cell. During the inverse latching period (S 130), the control signals CTRL 2 and CTRL 7 are activated to high levels. Responding to the high-leveled activation of the control signals CTRL 2 and CTRL 7, a logical condition of the latch node LN 3 is dependent on a voltage of the sensing node SN. For example, if the value of the program data is ‘0’ and the sensing node SN is set on high level (i.e., if the selected memory cell has been properly programmed), the latch node LN 3 is maintained on low level, i.e., logical ‘0’.
If the value of the program data is ‘0’ and the sensing node SN is set on low level (i.e., if the selected memory cell has a threshold voltage lower than a desired level, and has therefore not been properly programmed), the latch node LN 3 is maintained on low level, i.e., logical ‘0’. That is, if the value of the program data is ‘0’, the latch node LN 3 is maintained in the previous state during the inverse latching period. If the value of the program data is ‘1’ and the sensing node SN is set on low level (i.e., if a selected memory cell has been properly program-inhibited), the latch node LN 3 is maintained on logical ‘1’. If the value of the program data is ‘1’ and the sensing node SN is set on high level (i.e., if a program-inhibited memory cell has been programmed), the latch node LN 3 changes from ‘1’ to ‘0’.
In other words, only if the value of the program data is ‘1’ and the sensing node SN is set on high level, the latch node LN 3 changes from ‘1’ to ‘0’. Accordingly, as the latch node LN 3 is set to ‘1’ or ‘0’, the data line 302 maintains its precharged level, i.e., high level, through the data output circuit 360, or changes into low level. Logical conditions of the latch nodes LN 1 and LN 3 varying during the inverse latching period are illustrated in FIG. If the latch node LN 1 of the first register 320 is set on low level (i.e., a selected memory cell is a memory cell to be programmed, which is hereinafter referred to as ‘program memory cell’), the data line 302 is maintained at the precharged level regardless of a logical condition of the latch node LN 3 of the second register 330.
Conversely, if the latch node LN 1 of the first register 320 is set to high level (i.e., a selected memory cell is a memory cell to be program-inhibited), the data line 302 selectively changes dependent on a logical condition of the latch node LN 3 of the second register 330. If the latch node LN 1 of the first register 320 is set on high level while the latch node LN 3 of the second register 330 is set on low level, NMOS transistors M 13 and M 15 of the data output circuit 360 are turned on to change the data line 302 from high to low level. This indicates that a program-inhibited memory cell has been inadvertently programmed. As can be seen from the description above, when a memory cell corresponding to data ‘1’ is programmed into data ‘0’, the data line 302 changes during the inverse latching period. A voltage change of the data line 302 is determined by the detection circuit 400. A result of the detection is output to the control logic circuit 500. Thereafter, during the normal latching period (S 140), the control signals CTRL 3 and CTRL 7 are activated to high levels.
If the control signals CTRL 3 and CTRL 7 are activated to high levels, a logical condition of the latch node LN 3 changes according to a voltage of the sensing node SN. For instance, since the sensing node SN is set to high level if a selected memory cell is programmed in a desired threshold voltage or if a program-inhibited memory cell is programmed, the latch node LN 3 changes from ‘0’ to ‘1’. Otherwise, since the sensing node SN is set to low level if a selected memory cell is not programmed in the desired threshold voltage, the latch node LN 3 is maintained on ‘0’.
And, since the sensing node SN is set to low level if a selected memory cell is a program-inhibited memory cell, the latch node LN 3 is maintained on ‘1’. Logical conditions of the latch nodes LN 1 and LN 3 varying during the normal latching period are shown in FIG. Afterward, the control logic circuit 500 may determine whether a program-inhibited memory cell has been inadvertently programmed (S 150). This determination may be carried out according to a result from the detection circuit 400, i.e., a voltage variation of the data line 302. As previously described, if a program-inhibited memory cell is inadvertently programmed, the data line 302 changes to low level from high level. Thus, as a result of detecting a low level from the data line 302, it is determined that the program-inhibited memory cell has been accidentally programmed.
In this case, the procedure goes to operation S 190. In the operation S 190, the control logic circuit 500 arranges a result of this programming operation to status fail and ends the programming procedure. In response to a program-inhibited memory cell not being detected as being programmed, the procedure turns to operation S 160. In operation S 160, the control logic circuit 500 determines whether a selected memory cell to be programmed, i.e., a program memory cell, has been properly programmed. If the selected program memory cell is programmed successfully, the latch node LN 3 changes from ‘0’ to ‘1’. During this operation, the data line 302 is maintained on its precharging condition.
This circumstance is determined as a verification pass by the control logic circuit 500. Conversely, if the program memory cell is still not programmed, the latch node LN 3 is maintained at ‘0’. During this operation, the data line 302 is set to low level through the NMOS transistors M 13 and M 14 of the data output circuit 360. This change is determined as a verification fail by the control logic circuit 500. If a verification pass is determined in operation S 160, the procedure turns to S 180. In the operation S 180, the control logic circuit 500 arranges a result of the programming operation to status pass and terminates the programming procedure.
If a verification fail is determined from the operation S 160, the procedure goes to operation S 170. In operation S 170, the control logic circuit 500 determines whether a current count of the program loop has reached the maximum loop count. If the current count of the program loop is determined having reached the maximum, the procedure goes to operation S 190.
If the current count of the program loop is not determined to have reached the maximum, the procedure returns to operation S 110. The other operations subsequent to operation S 110 are the same as the aforementioned, and will therefore not be further described. According to the programming method of the flash memory device by the present general inventive concept, it is possible to determine or detect whether a program-inhibited memory cell has been programmed as data ‘0’.
Edc Samsung Execution Program
Additionally, insignificant repetition of the program loop when there is detected a program-inhibited memory cell programmed in data ‘0’ is prevented, reducing consumptive operations in the flash memory device. In another exemplary embodiment, it is permissible to variously modify a point of detecting a voltage change from the data line 302 affected by data latched in the page buffer 301 during the inverse latch period. For instance, such detection may precede the normal latch period. In yet another exemplary embodiment, the normal latch operation may be selectively conducted in accordance with a result of detecting a voltage variation from the data line 302. For instance, the normal latching operation can be carried out after determining whether the detected result of voltage variation from the data line 302 indicates that a program-inhibited memory cell has been inadvertently programmed. In other words, in the flow chart illustrated in FIG. 7, it is permissible to execute operation S 150 prior to operation S 140.
In still another exemplary embodiment, a data state latched during the inverse latch period may be complementary to a data state latched during the normal latch period for a program memory cell. In another exemplary embodiment, the detection circuit 400 may be implemented by means of a pass/fail checking circuit ordinarily known in the art. Moreover, the detection circuit 400 may be included in the control logic circuit 500. 9 is a flow chart illustrating a programming method for the flash memory device 1000 in accordance with another embodiment of the present invention.
Referring to FIG. 9, a block B 100 indicated by a broken line includes operations S 210, S 230, S 240, S 250, and S 260 corresponding respectively to operations S 110, S 120, S 140, S 160, and S 170 of FIG. A block B 200 indicated by a broken line includes operations S 270, S 280, and S 290 corresponding respectively to operations S 120, S 130, and S 150 of FIG.
According to the programming procedure illustrated in FIG. 9, whether a program-inhibited memory cell has been programmed (B 200) is determined after a normal verify-reading operation. The operations shown in FIG. 9 may be similar to those shown in FIG. 7, so will not be further described. Flash memory devices are types of nonvolatile memories capable of keeping data stored therein even without power supply.
With a rapid increase in the use of mobile apparatuses such as cellular phones, personal digital assistants (PDA), digital cameras, portable gaming consoles, and MP3 devices, the flash memory devices are widely employed as code storage, as well as data storage. The flash memory devices may be also utilized in home applications such as high-definition televisions (HDTV), digital versatile disks (DVD), routers, and global positioning systems (GPS).
A schematic structure of a computing system including the flash memory device of the present general inventive concept is illustrated in FIG. The computing system 2000 according to the present general inventive concept may be organized by including a microprocessor (CPU) 2100, a user interface 2200, a modem 2300 such as a baseband chipset, a memory controller 2400, and the flash memory device 2500, all of which are connected to each other by way of a bus 2001. The flash memory device 2500 may be configured substantially as same as that illustrated in FIG. In the flash memory device 2500, N-bit data (N is a positive integer) processed or to be processed by the microprocessor 2100 may be stored through the memory controller 2400. If the computing system 2000 shown in FIG. 10 is a kind of mobile apparatus, it may be further include a battery 2600 for supplying power thereto. Although not illustrated in FIG.
10, the computing system 2000 may be further equipped with an application chipset, a camera image processor (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor; i.e., CIS), a mobile DRAM, etc. The memory controller 2400 and the flash memory device 2500, for example, are able to constitute a solid state drive/disk (SSD) using a nonvolatile memory for storing data. An exemplary SSD is disclosed in U.S. Patent Publication No.
20, which is incorporated herein by reference. The memory controller 2400 and the flash memory device 2500 may also form a memory card using a nonvolatile memory to store data. 11 is a block diagram illustrating a memory system according to an embodiment of the present invention. The memory system illustrated in FIG. 11 may be a portable apparatus 4000. The portable apparatus 4000 may be an MP3 player, a video player, a combination video and audio player, etc.
As illustrated in FIG. 11, the portable apparatus 4000 includes a memory 4640 and a memory controller 4650. The memory 4640 and the memory controller 4650 may be similar to those illustrated FIG. 10, and therefore a detailed description thereof will be omitted. The portable apparatus 4000 may further include an encoder and decoder 4610, presentation components 4620, and an interface 4630.
Data (video, audio, etc.) processed by the encoder and decoder (EDC) 4610 can be input to the memory 4640, through the memory controller 4650, and output from the memory 4640. As illustrated by dotted lines in FIG. 11, data can also be input directly into the memory 4640 from the EDC 4610 and/or output directly into the EDC 4610 from the memory 4640. The EDC 4610 is able to encode data in order to store the data into the memory 4640. For instance, the EDC 4610 may be able to conduct an MP3 encoding operation with audio data in order to store the data in the memory 4640.
In another way, the EDC 4610 may be able to conduct an MPEG encoding operation (e.g., MPEG2, MPEG4, etc.) with video data in order to store the data in the memory 4640. Further, the EDC 4610 may include pluralities of encoders to encode data of other types in accordance with other data formats. For example, the EDC 4610 may include an MP3 encoder for audio data and an MPEG encoder for video data.
The EDC 4610 is also able to decode an output of the memory 4640. For instance, the EDC 4610 may be able to conduct an MP3 decoding operation with audio data output from the memory 4640.
In another way, the EDC 4610 may be able to conduct an MPEG decoding operation (e.g., MPEG2, MPEG4, etc.) with video data output from the memory 4640. Further, the EDC 4610 may include pluralities of decoders to decode data of other types in accordance with other data formats. For instance, the EDC 4610 may include an MP3 decoder for audio data and an MPEG decoder for video data.
It can be also understood that the EDC 4610 may only include decoders. For example, previously encoded data can be received by the EDC 4610 and passed to the memory controller 4650 and/or the memory 4640. The EDC 4610 may be able to receive data for encoding by way of the interface 4630 or receive preciously encoded data. The interface 4630 may accord to a known standard (e.g., firmware, USB, etc.). The interface 4630 may further include more one interface units. For instance, the interface 4630 may include a firmware interface, a USB interface, and so on. Data from the memory 4640 may be even output by way of the interface 4630.
The presentation components 4620 may be able to display data output from the memory and/or decoded by the EDC 4610. For instance, the presentation components 4620 may include a speaker jack for outputting audio data, a display screen for outputting video data, and so on. The flash memory and/or the memory controller according to the present invention can be mounted on the aforementioned system or apparatus by way of various types of packages.
. Mono Laser MFP SCX-340x series SCX-340x / 340xF / 340xW / 340xFW SERVICE MANUAL Mono Laser MFP Contents 1. Precautions 2. Product specification and description 3. Disassembly and Reassembly 4.
Alignment and Troubleshooting 5. System Diagram 6. Reference Information Refer to the service manual in the GSPN (see the rear cover) for more information. Fuser Unit.2 − 19 2.2.4.5. LSU (Laser Scanner Unit).2 − 21 2.2.4.6.
Toner Cartridge. 2 − 22 2.2.5. Hardware configuration.2 − 23 2.2.5.1. Main board.2 − 25 Copyright© 1995-2011 SAMSUNG. All rights reserved. Drive Unit.3 − 14 3.3.15. 3 − 15 3.3.16.
Feed Sensor PBA.3 − 16 3.3.17. Pick up roller.3 − 16 3.3.18. Motor.3 − 17 3.3.19. Transfer roller.3 − 18 Copyright© 1995-2011 SAMSUNG. All rights reserved. Periodic Defective Image.4 − 13 4.1.6. Useful management tools.4 − 14 4.1.6.1.
Using Samsung Easy Printer Manager (Windows and Macintosh only).4 − 14 4.1.6.2. Using Samsung Printer Status (Windows only).
4 − 16 4.1.6.3. High voltages and lasers inside this product are dangerous. This product should only be serviced by a factory trained service technician. 2) Use only Samsung replacement parts.
There are no user serviceable parts inside the product. Do not make any unauthorized changes or additions to the product as these could cause the product to malfunctions and create an electric shocks or fire hazards.
Take care not to cut or damage the power cable or plugs when moving the machine. 9) Use caution during thunder or lightning storms. Samsung recommends that this machine be disconnected from the power source when such weather conditions are expected. Do not touch the machine or the power cord if it is still connected to the wall socket in these weather conditions. Assembly and Disassembly precautions 1) Replace parts carefully and always use Samsung parts. Take care to note the exact location of parts and also cable routing before dismantling any part of the machine.
Ensure all parts and cables are replaced correctly. Please carry out the following procedures before dismantling the product or replacing any parts. 5) Do not install the printer on a sloping or unstable surface.
After installation, double check that the printer is stable. Copyright© 1995-2011 SAMSUNG. All rights reserved. 9) Minimize bodily motions when handling unpackaged replacement ESDs. Normal motions, such as the brushing together of clothing fabric and lifting one’s foot from a carpeted floor, can generate static electricity sufficient to damage an ESD. Copyright© 1995-2011 SAMSUNG.
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All rights reserved. Up to 20 ppm in A4 (21 ppm in Letter) Engine Speed Duplex Manual Duplex Warmup time From Sleep Less than 30 seconds From Ready Less than 8.5 seconds FPOT From Sleep Less than 15.5 seconds Copyright© 1995-2011 SAMSUNG. All rights reserved. Factory Default Text/Photo Platen Max. Original Size Legal (8.5' x 14') Multi Copy 199 Automatic Paper Selection Manual Paper Selection Duplex Copy Darkness Control 11 Levels Basic Copy Reduce & Enlarge 25% to 400% Copyright© 1995-2011 SAMSUNG. All rights reserved. 1 bit for Lineart & Halftone.
Mono 8 bits for Gray scale. Capacity 40 sheets @ 75 gsm.
Width: 142 216 mm Document Size. Length: 148 356 mm Copyright© 1995-2011 SAMSUNG. All rights reserved.
On hook Dial Search Yes (Phone Book) Speed Dial 200 locations Group Dial 100 Groups TAD I/F Telephone Features Tone/Pulse Yes (Selectable in Tech Mode) Pause Auto Redial Last Number Redial Caller ID External Phone Interface Copyright© 1995-2011 SAMSUNG. All rights reserved.
Product specification and description 2.1.2.5. Controller and Software Item Specification Processor 433 MHz SCX-340x/ 340xF/ 340xW: 64 MB. Std. SCX-340xFW: 128 MB.
Memory Memory expansion Printer Languages Fonts Windows Fonts Default Driver Install Windows 2000/ XP(32/64bits)/ Vista(32/64bits)/ 2003 Server(32/64bits)/. (SCX–340xW/ FW Supporting OS Same as wired network only) Samsung Easy Printer For Windows and Macintosh Manager Application For Linux Smart Panel SyncThru Web Service 2.0 Network Management Parallel Interface High speed USB 2.0 Copyright© 1995-2011 SAMSUNG. All rights reserved.
Sensing Optional Cassette Tray Face-Down: 100 sheets @ 80 g/m² Capacity. Output Stacking Output Full sensing Duplex Supporting 3 mm (0.12') from edge (Top, Bottom, Left, Right) Printable Area Non-Printable Area. Copyright© 1995-2011 SAMSUNG. All rights reserved.
JC97-03959A (ADF Unit) 20,000 Pages 2.1.2.9. Reliability and Service Items Specification Printing Volume (SET AMPV) 75 sheets/month MPBF 20,000 sheets MTTR 30 min. SET Life Cycle 30,000 sheets or 5 years (whichever comes first) Copyright© 1995-2011 SAMSUNG. All rights reserved. Product specification and description 2.1.2.10. Environment Item Specification. SCX-340x/ 340xW: 389 x 274 x 249 mm (15.3 x 10.8 x 9.8 inches).
SCX-340xF/ 340xFW: 402 x 293 x 296 mm (15.8 x Dimension (W x D x H) Machine 11.5 x 11.7 inches). Software CD The software CD contains the printer drivers and software applications. Accessories Miscellaneous accessories included with your machine may vary by country of purchase and specific model. Handset Handset model only Copyright© 1995-2011 SAMSUNG. All rights reserved. 150 Bin 150 CST 150 Bin Paper Output 100 sheet 50 sheet 100 sheet Capacity 40 sheet 35 sheet Noise 50 dBA 49 dBA 51 dBA Toner Cartridge 1.5K (0.7K) 1.5K (0.7K) 1.6K (0.7K) 2-11 Copyright© 1995-2011 SAMSUNG. All rights reserved.
Some features and optional goods may not be available depending on model or country. Type A Scanner lid Scanner glass Control panel Scan unit Tray Inner cover Tray handle Toner cartridge Output support Output tray Copyright© 1995-2011 SAMSUNG. All rights reserved. Document feeder output support Document feeder input support Control panel Document feeder input tray Handle Handset. Tray Scan unit Tray handle Inner cover Output support Toner cartridge Output tray. Handset model (SCX-340xFH) only 2-13 Copyright© 1995-2011 SAMSUNG. All rights reserved.
Some features and optional goods may not be available depending on model or country. Type A USB port Power receptacle Type B USB port Telephone line socket (Line) Network port Power receptacle Extension telephone socket (EXT) Copyright© 1995-2011 SAMSUNG. All rights reserved. Product specification and description 2.2.3. Paper Path The following diagram displays the path the paper follows during the printing process. ADF Engine 2-15 Copyright© 1995-2011 SAMSUNG.
All rights reserved. Pick up unit, Fuser, Bin-tray.
The hardware parts consists of the main board, SMPS/HVPS board, OPE board, PC interface. Toner cartridge Plate-Bottom Fuser unit Pick up roller Exit roller1 Feed roller Transfer roller Copyright© 1995-2011 SAMSUNG. All rights reserved. 2) Pick-up roller It has functions such as a paper pickup function, driving control function, paper feeding function, and removing electronic static function.
Pick up roller is driven by clutch. 2-17 Copyright© 1995-2011 SAMSUNG.
All rights reserved. Life Span: Print over 30,000 sheets (in 1530°C) 2.2.4.3. Drive Unit In SCX-340x series, the driving device consists of OPC, Pick- up, Feed, Fuser, Gear- Train connected with Mounting member. A step motor for driving is assembled to the left frame. 5) Halogen Lamp. Voltage: 120 V (115 ± 5%) / 220 V: 230 ± 5%. Capacity: 850 Watt ± 25 W 2-19 Copyright© 1995-2011 SAMSUNG.
All rights reserved. A fuser power is cut off when a front cover is opened. Maintain a temperature of fuser cover’s surface under 80°C for user, and attach a caution label at where customer can see easily when customer open a rear cover. Copyright© 1995-2011 SAMSUNG. All rights reserved. In other words, after the HSYNC signal is detected, the image data is sent to the LSU to adjust the left margin on paper.
The one side of the polygon mirror is one line for scanning. 2-21 Copyright© 1995-2011 SAMSUNG. All rights reserved. OPC Cleaning: Collect the toner by using cleaning blade. Handling of wasted toner: Collect the wasted toner in the cleaning frame by using cleaning blade. Classifying device for toner cartridge: ID is classified by CRUM Copyright© 1995-2011 SAMSUNG. All rights reserved.
SCX-340x series has a system board of integrated engine controller and video controller. The engine controller controls all modules required to print, that is, LSU, HVPS/SMPS, Fuser, Motor etc. It communicates with the video control block inside CPU for printing. And it has the interface for all video sync signal to print out the video data.
Product specification and description Circuit board locations The following diagrams show the locations of the printer circuit boards: Copyright© 1995-2011 SAMSUNG. All rights reserved. DDR2 128MB is adopted for high speed data processing. Boot has 8 MB SPI + 8 MB SPI. USB is the embedded type and wired network supports 100M full duplex.
Main board diagram 2-25 Copyright© 1995-2011 SAMSUNG. All rights reserved. Pick up connector USB device connector Fuser thermistor interface connector Scan motor connector Scan home sensor connector CIS interface connector. Information Part code: JC92–02433AG (SCX-340x) / JC92–02444AG (SCX-340xW) Part name: PBA-MAN Copyright© 1995-2011 SAMSUNG.
All rights reserved. USB device connector Fuser thermistor interface connector Scan motor connector ADF Module interface connector Scan home sensor connector CIS interface connector.
Information Part code: JC92–02434A (SCX-340xF) / JC92–02434B (SCX-340xFW) Part name: PBA-MAN 2-27 Copyright© 1995-2011 SAMSUNG. All rights reserved. OPE communicates with main controller via UART. The power LED is controlled by the main board.
OPE board diagram. OPE board image. Information Part code: JC92–02415A Part name: PBA-OPE. Connection Interface connector to main board Copyright© 1995-2011 SAMSUNG. All rights reserved. LED, Power LED, WPS LED, 16x2 Line LCD.
OPE communicates with main controller via UART. The power LED is controlled by the main board. OPE board diagram. OPE board image. Information Part code: JC92–02404A Part name: PBA-OPE. Connection Interface connector to main board 2-29 Copyright© 1995-2011 SAMSUNG.
Samsung Printer Edc Program Download
All rights reserved. The Wireless LAN Module supports 802.11b/g/n. It communicates with video controller via SPI.
WLAN board image. Information Part Code: JC92–02402A PBA name: PBA-WNPC. Connection Interface connector to main board (JC39-01565A, FFC CABLE-WLAN) Copyright© 1995-2011 SAMSUNG.
All rights reserved. Product specification and description 2.2.5.5. SMPS/HVPS board SCX-340x series has a power board of integrated SMPS and HVPS. The SMPS (Switching Mode Power Supply) Board supplies electric power to the Main Board and other boards through a Main Controller. The voltage provided includes +24V from a 110V/220V power input. HVPS PWMTHV HVPS VPPDEVAC HVPS Common Ground +24VS1 Relay, Fuser Common Ground Common Ground +24V SMPS RELAYON AC RELAY ON (ACTIVE HIGH) +24V SMPS Common Ground +24V SMPS FUSERON FUSERON (ACTIVE HIGH) Copyright© 1995-2011 SAMSUNG. All rights reserved.
Samsung Clp-310 Edc Program
Photo interrupter (Home Position sensor) Main board CIS detection Switch Front Cover SMP/HVPS board Cover open detection Photo interrupter (width Sensor) Main board Paper detection Photo interrupter (Feed Sensor) Main board Paper detection 2-33 Copyright© 1995-2011 SAMSUNG. All rights reserved. Product specification and description 2) Motor, Clutch Description ADF motor Scan motor Main motor Pick up Clutch Copyright© 1995-2011 SAMSUNG. All rights reserved.
AD converter. The voltage value for impressing to the transfer roller is decided by the changed value.
2-35 Copyright© 1995-2011 SAMSUNG. All rights reserved. Error Recovery: If the LReady or Hsync error happens, the paper is exited before the error code is initiated. The engine mode is changed to recovery mode and the engine informs the main system of the engine mode. The engine rechecks the LSU error, if the error does not reoccur printing is resumed.
Copyright© 1995-2011 SAMSUNG. All rights reserved. 2) Kernel controls and manage the whole procedure including Control flow and Printing Job before transferring to Engine system.
2-37 Copyright© 1995-2011 SAMSUNG. All rights reserved. 1) Network Interface Card is that relay the communication between Host and kernel using various network protocol. 2) Kernel is that manages the flow control of emulation procedure, receiving data from Host or Network card and printing with engine & rendering job.
Copyright© 1995-2011 SAMSUNG. All rights reserved. Kernel receives this data from Host, and then select emulation fit to data and start selected one. After emulation job end, Kernel sends the output bit-map data to Engine using Printer Video Controller (by clock type for LSU).
Engine print the received data to required paper with the sequential developing process. 2-39 Copyright© 1995-2011 SAMSUNG. All rights reserved.
Precautions when assembling and disassembling. Use only approved Samsung spare parts. Ensure that part number, product name, any voltage, current or temperature rating are correct. Failure to do so could result in damage to the machine, circuit overload, fire or electric shock. Many of the parts are held in place with plastic latches. The latches break easily; release them carefully. R18 drama cd. To remove such parts, press the hook end of the latch away from the part to which it is latched.
Copyright© 1995-2011 SAMSUNG. All rights reserved. Vijay tv tamil serials techsatish.
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